Mentor Graphics TestKompress Supports TSMC Reference Flow 6.0; Improves Test for Manufacturing Quality
WILSONVILLE, Ore.—(BUSINESS WIRE)—June 9, 2005—
Mentor Graphics Corporation (Nasdaq:MENT) today
announced that Taiwan Semiconductor Manufacturing Company (TSMC) has
added the TestKompress scan test tool to its Reference Flow 6.0.
TestKompress(R) provides an effective means of increasing volume
manufacturing test quality and reducing test cost for nanometer
designs. Reference Flow 6.0 also includes Mentor Graphics DFT tool
suite -- Fastscan(TM), MBISTArchitect(TM), and BSDArchitect(TM).
"Reference flow 6.0 has added new design-for-test technologies
that address specific nanometer needs," said Ed Wan, senior director
of design service marketing at TSMC. "The Mentor Graphics TestKompress
product provides increased test quality while reducing test data
volume, test time, and test cost."
The Mentor Graphics TestKompress embedded deterministic test
(EDT(TM)) tool reduces both manufacturing test time and test data
volume by up to 100X, helping users increase test coverage and test
quality on their complex devices. This compression enables
manufacturers to run a large battery of tests without slowing test
time, thereby maintaining a low cost of test. The tool also features
robust x-state tolerance that eliminates the need to either add
functional logic or adhere to strict design requirements imposed by
the test structures. In addition, the TestKompress tool fits well into
any scan-based methodology, and features a usage methodology that is
intuitive to engineers familiar with traditional ATPG.
Both TestKompress and FastScan feature advanced at-speed test
capabilities to improve detection of speed-related defects found at
smaller process technologies. TSMC has also added the MBISTArchitect
and BSDArchitect tools from Mentor Graphics to provide a complete
design for test (DFT) tool set in Reference Flow 6.0. MBISTArchitect
provides at-speed test of embedded memories operating up to 1GHz;
BSDArchitect is used to insert IEEE 1149.1 boundary scan that enables
in-circuit test.
"TSMC is an industry leader in meeting the challenges inherent in
volume manufacturing of complex nanometer devices," said Robert Hum,
vice president and general manager of the Design Verification and Test
division for Mentor Graphics. "We are very pleased that Mentor DFT
tools have been added to TSMC's Reference Flow 6.0 to meet the
specific challenges of cost-effective nanometer production test and
improve manufacturing test quality."
About Mentor Graphics Design-for-Test Tools
Mentor Graphics provides the industry's broadest portfolio of DFT
solutions for today's System-on-Chip and deep submicron designs,
including integrated solutions for scan, ATPG, EDT, advanced memory
test, boundary scan, logic built-in self-test and a variety of
DFT-related flows. For more information visit:
www.mentor.com/products/dft.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in
electronic hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronics and semiconductor companies. Established in
1981, the company reported revenues over the last 12 months of over
$700 million and employs approximately 3,850 people worldwide.
Corporate headquarters are located at 8005 S.W. Boeckman Road,
Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are
located at 1001 Ridder Park Drive, San Jose, California 95131-2314.
World Wide Web site: http://www.mentor.com/.
Mentor Graphics and TestKompress are registered trademarks of
Mentor Graphics Corporation. All other company or product names are
the registered trademarks or trademarks of their respective owners.
Contact:
Mentor Graphics Corporation, Wilsonville
Nate James, 503-685-0449
Email Contact
Suzanne Graham, 503-685-7789
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